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91207hkim 20070810-s00010 no. a0928-1/22 semiconductor components industries, llc, 2013 may, 2013 ver.1.00 http://onsemi.com lc87f5r96b overview the lc87f5r96b is an 8-bit microcomputer that, centered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 98k-byte flash rom (onboard programmable), 4096-byte ram, on-chip debugging function, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided in to 8-bit timers/counters or 8- bit pwms), four 8-bit timers with a prescaler, a base timer serving as a time-of-day cloc k, a high-speed clock counter, a synchronous sio interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous sio port, two uart ports (full duplex), an 8-bit 11-channel ad converter, two 12-bit pwm channels, a system clock frequency divider, and a 27-source 10-vector interrupt feature. features ? flash rom ? capable of on-board-programing with wide range, 2.7 to 5.5v, of voltage source ? block-erasable in 128 byte units ? 100352 8 bits (address: 00000h to 17fffh, 1f800h to 1ffffh) ? ram ? 4096 9 bits ? minimum bus cycle time ? 83.3ns (12mhz) v dd =2.8 to 5.5v ? 125ns (8mhz) v dd =2.5 to 5.5v ? 500ns (2mhz) v dd =2.2 to 5.5v note: the bus cycle time here refers to the rom read speed. ? minimum instruction cycle time (tcyc) ? 250ns (12mhz) v dd =2.8 to 5.5v ? 375ns (8mhz) v dd =2.5 to 5.5v ? 1.5 s (2mhz) v dd =2.2 to 5.5v ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1-bit units 46 (p1n, p2n, p3n, p70 to p73, p80 to p86, pcn, pwm2, pwm3, xt2) ports whose i/o direction can be designated in 4-bit units 8 (p0n) ? normal withstand voltage input port 1 (xt1) ? dedicated oscillator ports 2 (cf1, cf2) ? reset pins 1 (res ) ? power pins 6 (v ss 1 to 3, v dd 1 to 3) ordering number : ENA0928 * this product is licensed from silicon storage technology, inc. (usa). ordering number : ENA0928 cmos ic from 98k byte, ram 4096 byte on-chip 8-bit 1-chip microcontroller
lc87f5r96b no.a0928-2/22 ? timers ? timer 0: 16-bit timer/counter with a capture register mode 0: 8-bit timer with an 8-bit programmab le prescaler (with an 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmab le prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programmabl e prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible fr om the lower-order 8-bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes. ? high-speed clock counter 1) can count clocks with a maximum clock rate of 24mhz (at a main clock of 12mhz). 2) can generate output real-time. ? sio ? sio0: 8-bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tcyc) 3) automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) ? sio1: 8-bit asynchronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? uart: 2 channels ? full duplex ? 7/8/9 bit data bits selectable ? 1 stop bit (2 bit in continuous data transmission) ? built-in baudrate generator (with ba udrates of 16/3 to 8192/3 tcyc) ? ad converter: 8 bits 11 channels ? pwm: multifrequency 12-bit pwm 2 channels ? remote control receiver circuit (sharing pins with p73, int3, and t0in) 1) noise filtering function (noise filter time constant selectable from 1 tcyc, 32 tcyc, and 128 tcyc) 2) the noise filtering function is available for the int3, t0 in, or t0hcp signal at p73. when p73 is read with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function. ? watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable
lc87f5r96b no.a0928-3/22 ? clock output function 1) able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) able to output oscillation clock of sub clock. ? interrupts ? 27 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and hi ghest (x)) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interr upts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer0/base timer1 5 00023h h or l t0h/int6 6 0002bh h or l t1l/t1h/int7 7 00033h h or l sio0/uart1 receive/uart2 receive 8 0003bh h or l sio/uart1 transmit/uart2 transmit 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/t4/t5/pwm2, pwm3 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 2048 levels (the stack is allocated in ram) ? high-speed multiplication/division instructions ? 16-bits 8-bits (5 tcyc execution time) ? 24-bits 16-bits (12 tcyc execution time) ? 16-bits 8-bits (8 tcyc execution time) ? 24-bits 16-bits (12 tcyc execution time) ? oscillation circuits ? rc oscillation circuit (internal) : for system clock ? cf oscillation circuit : for system clock, with internal rf ? crystal oscillation circuit : for low-speed system clock ? multifrequency rc oscillation circu it (internal) : for system clock ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 250ns, 500ns, 1.0 s, 2.0 s, 4.0 s, 8.0 s, 16.0 s, 32.0 s, and 64.0 s (at a main clock rate of 12mhz).
lc87f5r96b no.a0928-4/22 ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) canceled by a system reset or occurrence of an interrupt. ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc, and crystal oscilla tors automatically stop operation. 2) there are three ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) setting at least one of the int0, int1, int2 , int4, and int5 pins to the specified level (3) having an interrupt source established at port 0 ? x'tal hold mode: suspends instruction execution and the oper ation of the peripheral circuits except the base timer. 1) the cf and rc oscillators automatically stop operation. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are four ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, int2 , int4, and int5 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established in the base timer circuit ? on-chip debugger function ? permits software debugging with the test device installed on the target board. ? package form ? qip64e (14 14 ) : ?lead-free type? ? development tools ? evaluation (eva) chip : lc87ev690 ? emulator : eva62s + ecb876600d + sub875m00 + pod64qfp ice-b877300 + sub875m00 + pod64qfp ? on-chip-debugger : tcb87-typeb + lc87f5r96b ? programming boards package programming boards qip64e(14 14 ) w87f50256q ? flash rom programmer maker model support version(note) device flash support group, inc.(single) af9708/09/09b (including product of ando electric co.,ltd) revision : after rev.02.73 lc87f76c8a flash support group, inc.(gang) af9723(main body) (including product of ando electric co.,ltd) revision : after rev.02.29 lc87f5nc8a af9833(unit) (including product of ando electric co.,ltd) revision : after rev.01.88 our company skk/skk type-b/skk dbg type-b (sanyo fws) application version: after 1.04 chip data version: after2.11 lc87f5r96b
lc87f5r96b no.a0928-5/22 package dimensions unit : mm (typ) 3159a pin assignment qip64e(14 14) ?lead-free type? sanyo : qip64e(14x14) 14.0 17.2 14.0 17.2 0.15 0.35 0.8 (2.7) 3.0max 0.1 0.8 (1.0) 116 17 32 33 48 49 64 lc87f5r96b top view p83/an3 p84/an4 p85/an5 p86/an6 pc0 pc1 pc2 pc3 pc4 pc5/dbgp0 pc6/dbgp1 pc7/dbgp2 v dd 3 v ss 3 p30 p31 p32/utx1 p33/urx1 p34/utx2 p35/urx2 p36 p37 p27/int5/t1in p26/int5/t1in p25/int5/t1in p24/int5/t1in/int7 p23/int4/t1in p22/int4/t1in p21/int4/t1in p20/int4/t1in/int6 p07/t7o p06/t6o p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/nkin p73/int3/t0in res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz pwm2 pwm3 v dd 2 v ss 2 p00 p01 p02 p03 p04 p05/cko 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 4 8 47 4 6 4 5 44 4 3 42 41 4 0 39 38 3 7 36 35 3 4 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
lc87f5r96b no.a0928-6/22 system block diagram interrupt control standby control ir pla bus interface port 0 port 1 sio0 sio1 timer 0 timer 1 timer 4 timer 5 port 2 port 7 port 8 adc alu flash rom pc acc b register c register psw rar ram stack pointer watchdog timer pwm2/3 uart1 base timer timer 6 int0 to int7 noise filter timer 7 port 3 port c uart2 on-chip debugger cf rc x?tal clock generator mrc
lc87f5r96b no.a0928-7/22 pin description pin name i/o description option v ss 1, v ss 2 v ss 3 - - power supply pin no v dd 1, v dd 2 v dd 3 - + power supply pin no port 0 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistor can be turned on and off in 4-bit units ? hold release input ? port 0 interrupt input ? shared pins p05: clock output (system clock/can selected from sub clock) p06: timer 6 toggle output p07: timer 7 toggle output yes p00 to p07 port 1 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: timer 1 pwml output p17: timer 1 pwmh output/beeper output yes p10 to p17 port 2 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? other functions p20: int4 input/hold reset input/timer 1 event input/timer 0l capture input/ timer 0h capture input/int6 input/timer 0l capture 1 input p21 to p23: int4 input/hold reset input/timer 1 event in put/timer 0l capture input/ timer 0h capture input p24: int5 input/hold reset input/timer 1 event input/timer 0l capture input/ timer 0h capture input/int7 input/timer 0h capture 1 input p25 to p27: int5 input/hold reset input/timer 1 event in put/timer 0l capture input/ timer 0h capture input ? interrupt acknowledge type yes p20 to p27 rising falling rising/ falling h level l level int4 int5 int6 int7 enable enable enable enable enable enable enable enable enable enable enable enable disable disable disable disable disable disable disable disable continued on next page.
lc87f5r96b no.a0928-8/22 continued from preceding page. pin name i/o description option port 7 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? shared pins p70: int0 input/hold reset input/time r 0l capture input/watchdog timer output p71: int1 input/hold reset input/timer 0h capture input p72: int2 input/hold reset input/timer 0 event input/timer 0l capture input/ high speed clock counter input p73: int3 input (with noise filter)/time r 0 event input/timer 0h capture input ad converter input port: an8 (p70), an9 (p71) ? interrupt acknowledge type no p70 to p73 rising falling rising/ falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable port 8 i/o ? 7-bit i/o port ? i/o specifiable in 1-bit units ? shared pins ad converter input port : an0 (p80) to an6 (p86) no p80 to p86 pwm2 pwm3 i/o ? pwm2 and pwm3 output ports ? general-purpose i/o available no port 3 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions p32: uart1 transmit p33: uart1 receive p34: uart2 transmit p35: uart2 receive yes p30 to p37 port c i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions dbgp0 to dbgp2(pc5 to pc7): on-chip debugger yes pc0 to pc7 res input reset pin no xt1 input ? 32.768khz crystal oscillator input pin ? shared pins general-purpose input port ad converter input port : an10 must be connected to v dd 1 if not to be used. no xt2 i/o ? 32.768khz crystal oscillator input pin ? shared pins general-purpose i/o port ad converter input port : an11 must be set for oscillation and kept open if not to be used. no cf1 input ceramic resonator input pin no cf2 output ceramic resonator output pin no
lc87f5r96b no.a0928-9/22 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port options selected in units of option type output type pull-up resistor p00 to p07 1 bit 1 cmos programmable (note 1) 2 nch-open drain no p10 to p17 1 bit 1 cmos programmable 2 nch-open drain programmable p20 to p27 1 bit 1 cmos programmable 2 nch-open drain programmable p30 to p37 1 bit 1 cmos programmable 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable p80 to p86 - no nch-open drain no pwm2, pwm3 - no cmos no pc0 to pc7 1 bit 1 cmos programmable 2 nch-open drain programmable xt1 - no input for 32.768khz crystal oscillator (input only) no xt2 - no output for 32.768khz crystal oscillator (nch-open drain when in general-purpose output mode) no note 1: programmable pull-up resistors for port 0 are controlled in 4-bit units (p00 to 03, p04 to 07). *1: make the following connection to minimize the noise input to the v dd 1 pin and prolong the backup time. be sure to electrically short the v ss 1, v ss 2, and v ss 3 pins. (example 1) when backup is active in the hold mode, the high level of the port outputs is supplied by the backup capacitors. (example 2) the high-level output at the ports is unstable when the hold m ode backup is in effect. lsi power supply v ss 1 back-up capacitor v ss 2 v ss 3 v dd 3 v dd 2 v dd 1 v dd 3 v dd 2 v dd 1 lsi v ss 1v ss 2v ss 3 back-up capacitor power supply
lc87f5r96b no.a0928-10/22 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pins/remarks conditions specification v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3v dd 1=v dd 2=v dd 3 -0.3 +6.5 v input voltage v i (1) xt1, cf1 -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2 ports 7, 8 ports 3, c pwm0, pwm1, xt2 -0.3 v dd +0.3 high level output current peak output current ioph(1) ports 0, 1, 2 ports 3, c cmos output select per 1 application pin -10 ma ioph(2) pwm2, pwm3 per 1 application pin. -20 ioph(3) p71 to p73 per 1 application pin. -5 mean output current (note1-1) iomh(1) ports 0, 1, 2 ports 3, c cmos output select per 1 application pin -7.5 iomh(2) pwm2, pwm3 per 1 application pin -10 iomh(3) p71 to p73 per 1 application pin -3 total output current ioah(1) p71 to p73 total of all applicable pins -10 ioah(2) port 1 pwm2, pwm3 total of all applicable pins -25 ioah(3) ports 0, 2 total of all applicable pins -25 ioah(4) ports 0, 1, 2 pwm2, pwm3 total of all applicable pins -45 ioah(5) port 3 total of all applicable pins -25 ioah(6) port c total of all applicable pins -25 ioah(7) ports 3, c total of all applicable pins -45 low level output current peak output current iopl(1) p02 to p07 ports 1, 2 ports 3, c pwm2, pwm3 per 1 application pin. 20 iopl(2) p00, p01 per 1 application pin. 30 iopl(3) ports 7, 8, xt2 per 1 application pin. 10 mean output current (note1-1) ioml(1) p02 to p07 ports 1, 2 ports 3, c pwm2, pwm3 per 1 application pin. 15 ioml(2) p00, p01 per 1 application pin. 20 ioml(3) ports 7, 8, xt2 per 1 application pin. 7.5 total output current ioal(1) port 7 p83 to p86, xt2 total of all applicable pins 15 ioal(2) p80 to p82 total of all applicable pins 15 ioal(3) ports 7, 8, xt2 total of all applicable pins 20 ioal(4) port 1 pwm2, pwm3 total of all applicable pins 45 ioal(5) ports 0, 2 total of all applicable pins 45 ioal(6) ports 0, 1, 2 pwm2, pwm3 total of all applicable pins 80 ioal(7) port 3 total of all applicable pins 45 ioal(8) port c total of all applicable pins 45 ioal(9) ports 3, c total of all applicable pins 80 power dissipation pd max qip64e(14 14) ta=-40 to +85 c 300 mw operating ambient temperature topr -40 +85 c storage ambient temperature tstg -55 +125 note 1-1: the mean output current is a mean value measured over 100ms. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lc87f5r96b no.a0928-11/22 allowable operating conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pins/remarks conditions specification v dd [v] min typ max unit operating supply voltage (note2-1) v dd (1) v dd 1=v dd 2=v dd 3 0.245 s tcyc 200 s 2.8 5.5 v 0.367 s tcyc 200 s 2.5 5.5 1.47 s tcyc 200 s 2.2 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode 2.0 5.5 high level input voltage v ih (1) ports 1, 2 p71 to p73 p70 port input/ interrupt side 2.2 to 5.5 0.3v dd +0.7 v dd v ih (2) ports 0, 8, 3, c pwm2, pwm3 2.2 to 5.5 0.3v dd +0.7 v dd v ih (3) port p70 watchdog timer side 2.2 to 5.5 0.9v dd v dd v ih (4) xt1, xt2, cf1, res 2.2 to 5.5 0.75v dd v dd low level input voltage v il (1) ports 1, 2 p71 to p73 p70 port input/ interrupt side 4.0 to 5.5 v ss 0.1v dd +0.4 2.2 to 4.0 v ss 0.2v dd v il (2) ports 0, 8, 3, c pwm2, pwm3 4.0 to 5.5 v ss 0.15v dd +0.4 2.2 to 5.5 v ss 0.2v dd v il (3) port 70 watchdog timer side 2.2 to 5.5 v ss 0.8v dd -1.0 v il (4) xt1, xt2, cf1, res 2.2 to 5.5 v ss 0.25v dd instruction cycle time (note2-2) tcyc 2.8 to 5.5 0.245 200 s 2.5 to 5.5 0.367 200 2.2 to 5.5 1.47 200 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division rate=1/1 ? external system clock duty=505% 2.8 to 5.5 0.1 12 mhz 2.5 to 5.5 0.1 8 2.2 to 5.5 0.1 2 ? cf2 pin open ? system clock frequency division rate=1/2 2.8 to 5.5 0.2 24.4 2.5 to 5.5 0.1 16 2.2 to 5.5 0.1 4 oscillation frequency range (note2-3) fmcf(1) cf1, cf2 12mhz ceramic oscillation see fig. 1. 2.8 to 5.5 12 mhz fmcf(2) cf1, cf2 8mhz ceramic oscillation see fig. 1. 2.5 to 5.5 8 fmcf(3) cf1, cf2 4mhz ceramic oscillation see fig. 1. 2.2 to 5.5 4 fmrc internal rc oscillation 2.2 to 5.5 0.3 1.0 2.0 fmmrc frequency variable rc oscillation source oscillation 2.5 to 5.5 16 fsx?tal xt1, xt2 32.768khz crystal oscillation see fig. 2. 2.2 to 5.5 32.768 khz note 2-1: v dd must be held greater than or equal to 2.7v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants.
lc87f5r96b no.a0928-12/22 electrical characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pins/remarks conditions specification v dd [v] min typ max unit high level input current i ih (1) ports 0, 1, 2 ports 7, 8 ports 3, c res pwm2, pwm3 output disabled pull-up resistor off v in =v dd (including output tr's off leakage current)) 2.2 to 5.5 1 a i ih (2) xt1, xt2 for input port specification v in =v dd 2.2 to 5.5 1 i ih (3) cf1 v in =v dd 2.2 to 5.5 15 low level input current i il (1) ports 0, 1, 2 ports 7, 8 ports 3, c res pwm2, pwm3 output disabled pull-up resistor off v in =v ss (including output tr's off leakage current)) 2.2 to 5.5 -1 i il (2) xt1, xt2 for input port specification v in =v ss 2.2 to 5.5 -1 i il (3) cf1 v in =v ss 2.2 to 5.5 -15 high level output voltage v oh (1) ports 0, 1, 2 ports 3, c i oh =-1ma 4.5 to 5.5 v dd -1 v v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (4) ports 71 to 73 i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (5) i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (6) pwm2, pwm3 i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (7) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 v oh (8) i oh =-1ma 2.2 to 5.5 v dd -0.4 low level output voltage v ol (1) ports 0, 1, 2 ports 3, c pwm2, pwm3, i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.6ma 3.0 to 5.5 0.4 v ol (3) i ol =1ma 2.2 to 5.5 0.4 v ol (4) ports 7, 8 xt2 i ol =1.6ma 3.0 to 5.5 0.4 v ol (5) i ol =1ma 2.2 to 5.5 0.4 v ol (6) p00, p01 i ol =30ma 4.5 to 5.5 1.5 v ol (7) i ol =5ma 3.0 to 5.5 0.4 v ol (8) i ol =2.5ma 2.2 to 5.5 0.4 pull-up resistance rpu(1) ports 0, 1, 2, 7 ports 3, c v oh =0.9v dd 4.5 to 5.5 15 35 80 k rpu(2) 2.2 to 5.5 18 35 150 hysteresis voltage vhys res ports 1, 2, 7 2.2to 5.5 0.1v dd v pin capacitance cp all pins ? for pins other than that under test: v in =v ss ? f=1mhz ? ta=25c 2.2 to 5.5 10 pf
lc87f5r96b no.a0928-13/22 serial i/o characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) parameter symbol pins /remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(1) sck0(p12) ? see fig. 6. 2.2 to 5.5 2 tcyc low level pulse width tsckl(1) 1 high level pulse width tsckh(1) 1 tsckha(1) ? continuous data transmission/reception mode ? see fig. 6. ? (note 4-1-2) 4 output clock frequency tsck(2) sck0(p12) ? cmos output selected ? see fig. 6. 2.2 to 5.5 4/3 low level pulse width tsckl(2) 1/2 tsck high level pulse width tsckh(2) 1/2 tsckha(2) ? continuous data transmission/reception mode ? cmos output selected ? see fig. 6. tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tcyc serial input data setup time tsdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk ? see fig. 6. 2.2 to 5.5 0.03 s data hold time thdi(1) 2.2 to 5.5 0.03 serial output input clock output delay time tdd0(1) so0(p10), sb0(p11), ? continuous data transmission/reception mode ? (note 4-1-3) 2.2 to 5.5 (1/3)tcyc +0.05 tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 2.2 to 5.5 1tcyc +0.05 output clock tdd0(3) ? (note 4-1-3) 2.2 to 5.5 (1/3)tcyc +0.15 note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
lc87f5r96b no.a0928-14/22 2. sio1 serial i/o characteristics (note 4-2-1) parameter symbol pins/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(3) sck1(p15) ? see fig. 6. 2.2 to 5.5 2 tcyc low level pulse width tsckl(3) 1 high level pulse width tsckh(3) 1 output clock frequency tsck(4) sck1(p15) ? cmos output selected. ? see fig. 6. 2.2 to 5.5 2 low level pulse width tsckl(4) 1/2 tsck high level pulse width tsckh(4) 1/2 serial input data setup time tsdi(2) sb1(p14) si1(p14), ? must be specified with respect to rising edge of sioclk ? see fig. 6. 2.2 to 5.5 0.03 s data hold time thdi(2) 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.2 to 5.5 (1/3)tcyc +0.05 note 4-2-1: these specifications are theoretical values. add margin depending on its use.
lc87f5r96b no.a0928-15/22 pulse input conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pins/remarks conditions specification v dd [v] min typ max unit high/low level pulse width tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) int4(p20 to p23), int5(p24 to p27), int6(p20) int7(p24) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.2 to 5.5 1 tcyc tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1. ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 256 tpil(5) res resetting is enabled. 2.2 to 5.5 200 s ad converter characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pins/remarks conditions specification v dd [v] min typ max unit resolution n an0(p80) to an6(p86), an8(p70), an9(p71), an10(xt1), an11(xt2), 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 1.5 lsb conversion time tcad ad conversion time=32 tcyc (when adcr2=0) (note 6-2) 4.5 to 5.5 11.74 (tcyc= 0.367 s) 97.92 (tcyc= 3.06 s) s 3.0 to 5.5 23.53 (tcyc= 0.735 s) 97.92 (tcyc= 3.06 s) ad conversion time=64 tcyc (when adcr2=1) (note 6-2) 4.5 to 5.5 15.68 (tcyc= 0.245 s) 97.92 (tcyc= 1.53 s) 3.0 to 5.5 23.49 (tcyc= 0.376 s) 97.92 (tcyc= 1.53 s) analog input voltage range vain 3.0 to 5.5 v ss v dd v analog port input current iainh vain=v dd 3.0 to 5.5 1 a iainl vain=v ss 3.0 to 5.5 -1 note 6-1: the quantization error ( 1/2 lsb) is excluded from th e absolute accuracy value. note 6-2: the conversion time refers to the interval from th e time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register.
lc87f5r96b no.a0928-16/22 consumption current characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pins/remarks conditions specification v dd [v] min typ max unit normal mode consumption current (note 7-1) iddop(1) v dd 1 =v dd 2 =v dd 3 ? fmcf=12mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 4.5 to 5.5 9.1 18.5 ma 2.8 to 4.5 5.3 13.5 iddop(2) ? fmcf=8mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 4.5 to 5.5 6.7 14 iddop(3) 2.5 to 4.5 3.8 10 iddop(4) ? fmcf=4mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 4.5 to 5.5 2.7 6 iddop(5) 2.2 to 4.5 1.45 3.8 iddop(6) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped ?1/2 frequency division ratio. 4.5 to 5.5 0.95 4.3 iddop(7) 2.2 to 4.5 0.53 3.0 iddop(8) ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768khz by crystal oscillation mode. ? system clock set to 1mhz with frequency variable rc oscillation ? internal rc oscillation stopped ? 1/2 frequency division ratio. 4.5 to 5.5 1.25 5.2 iddop(9) 2.2 to 4.5 0.67 4.2 iddop(10) ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768khz by crystal oscillation mode. ? system clock set to 32.768khz side. ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 4.5 to 5.5 38 112 a iddop(11) 2.2 to 4.5 19 72 halt mode consumption current (note 7-1) iddhalt(1) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 4.5 to 5.5 3.2 7.5 ma 2.8 to 5.5 1.8 4 iddhalt(2) ? halt mode ? fmcf=8mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 4.5 to 5.5 2.4 5.3 iddhalt(3) 2.5 to 4.5 12.5 2.8 note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors continued on next page.
lc87f5r96b no.a0928-17/22 continued from preceding page. parameter symbol pins/remarks conditions specification v dd [v] min typ max unit halt mode consumption current (note 7-1) iddhalt(4) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=4mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 4.5 to 5.5 1 2.3 ma iddhalt(5) 2.2 to 4.5 0.5 1.3 iddhalt(6) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped ?1/2 frequency division ratio. 4.5 to 5.5 0.33 0.9 iddhalt(7) 2.2 to 4.5 0.17 0.7 iddhalt(8) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768khz by crystal oscillation mode. ? system clock set to 1mhz with frequency variable rc oscillation ? internal rc oscillation stopped ? 1/2 frequency division ratio. 4.5 to 5.5 1 3.8 iddhalt(9) 2.2 to 4.5 0.5 2.7 iddhalt(10) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx'tal=32.768khz by crystal oscillation mode. ? system clock set to 32.768khz side. ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 4.5 to 5.5 18 73 a iddhalt(11) 2.2 to 4.5 5 65 hold mode consumption current iddhold(1) v dd 1 ? hold mode ? cf1=v dd or open (external clock mode) 4.5 to 5.5 0.035 20 iddhold(2) 2.2 to 4.5 0.015 16 timer hold mode consumption current iddhold(3) ? timer hold mode ? cf1=v dd or open (external clock mode) ? fmx'tal=32.768khz by crystal oscillation mode 4.5 to 5.5 16 65 iddhold(4) 2.2 to 4.5 3.5 52 note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors f-rom programming characteristics at ta = +10c to +55c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pins/remarks conditions specification v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? without cpu current 2.70 to 5.5 5 10 ma programming time tfw(1) ? erasing 2.7 to 5.5 20 30 ms tfw(2) ? programming 2.7 to 5.5 40 60 s
lc87f5r96b no.a0928-18/22 uart (full duplex) op erating conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pins/remarks conditions specification v dd [v] min typ max unit transfer rate ubr p32 (utx1), p33 (urx1), p34 (utx2), p35 (urx2) 2.5 to 5.5 16/3 8192/3 tcyc data length : 7/8/9 bits (lsb first) stop bits : 1-bit (2-bit in continuous data transmission) parity bits : none example of continuous 8-bit data transmission mode processing (first transmit data = 55h) example of continuous 8-bit da ta reception mode processing (first receive data = 55h) v dd 1, v ss 1 terminal condition it is necessary to place capacitors between v dd 1 and v ss 1 as describe below. ? place capacitors as close to v dd 1 and v ss 1 as possible. ? place capacitors so that the length of each terminal to th e each leg of the capacitor be equal (l1 = l1?, l2 = l2?). ? place high capacitance capacitor c1 and lo w capacitance capacitor c2 in parallel. ? capacitance of c2 must be more than 0.1 f. ? use thicker pattern for v dd 1 and v ss 1. transmit data (lsb first) start of transmission end of transmission ubr start bit stop bit ubr receive data (lsb first) start of reception end of reception start bit stop bit v ss 1 v dd 1 l1? l2? l1 l2 c1 c2
lc87f5r96b no.a0928-19/22 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main system clock oscillation circuit that are measured using a our designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf1 [ ] rd1 [ ] typ [ms] max [ms] 12mhz murata cstce12m0g52-r0 (10) (10) open 470 2.6 to 5.5 0.03 0.5 internal c1,c2 10mhz cstce10m0g52-r0 (10) (10) open 470 2.4 to 5.5 0.03 0.5 internal c1,c2 cstls10m0g53-b0 (15) (15) open 680 2.6 to 5.5 0.03 0.5 internal c1,c2 8mhz cstce8m00g52-r0 (10) (10) open 680 2.3 to 5.5 0.03 0.5 internal c1,c2 cstls8m00g53-b0 (15) (15) open 1k 2.5 to 5.5 0.03 0.5 internal c1,c2 4mhz cstcr4m00g53-r0 (15) (15) open 1.5k 2.2 to 5.5 0.03 0.5 internal c1,c2 cstls4m00g53-b0 (15) (15) open 1.5k 2.2 to 5.5 0.03 0.5 internal c1,c2 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see fig. 4). characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a our designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c3 [pf] c4 [pf] rf2 [ ] rd2 [ ] typ [s] max [s] 32.768khz seiko toyocom mc-306 18 18 open 560k 2.2 to 5.5 1.2 3.0 applicable cl value=12.5pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see figure. 4). note: the components that are involved in oscillation should be placed as close to the ic and to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit figure 3 ac timing measurement point 0.5v dd c3 rd2 c4 x?tal xt2 xt1 rf2 c1 c2 cf cf2 cf1 rd1 rf1
lc87f5r96b no.a0928-20/22 reset time and oscillation stabilization time hold release signal and oscillation stabilization time figure 4 oscillation stabilization times operating v dd lower limit power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd 0v hold reset signal internal rc oscillation cf1, cf2 xt1, xt2 state hold reset signal valid tmscf tmsx?tal hold halt hold reset signal absent
lc87f5r96b no.a0928-21/22 figure 5 reset circuit figure 6 serial i/o waveforms figure 7 pulse input timing signal waveform c res v dd r res res note: determine the value of c res and r res so that the reset signal is present for a period of 200 s after the supply voltage goes beyond the lower limit of the ic?s operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckla tsckha thdi tsdi tddo data ram transfer period (sio0 only) data ram transfer period (sio0 only)
lc87f5r96b no.a0928-22/22 ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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